The schedule for the presentation of the demos is as follows:


Tuesday  June 26th Wednesday  June 27th Thursday  June 28th
Morning Setting up demos Demos presentation Demos presentation
Afternoon Demos presentation Uninstalling demos
Evening Best demo award ceremony

Demonstrations to be presented at ICT 2018

Demonstration 1: Deep Learning-Based Communication Over the Air; The world’s first communications system entirely based on neural networks

Presenter: Dr. Jakob HOYDIS (

Description: We have introduced a new way of thinking about communications as an end-to-end reconstruction optimization task using autoencoders to jointly learn transmitter and receiver implementations without prior knowledge. This approach is applicable to any type of channel and shown to achieve competitive performance with respect to state-of-the-art schemes on real hardware. We believe that this is just the beginning of a much more comprehensive study into applications of deep learning for the physical layer. We are truly excited about the possibilities it could lend towards future communications systems as the field matures.

Demonstration 2: Multi-Armed bandit Learning in Iot Networks (MALIN)

Presenters: Rémi Bonnefoi (1), Lilian Besson (1)(2) and Christophe Moy (3)
(1) CentraleSupélec/IETR , 35576, Cesson-Sévigné Cedex, France
(2) Univ Lille, CNRS, INRIA, SequeL Team, UMR 9189 – CRIStAL, F-59000 Lille, France
(3) Univ Rennes, CNRS, IETR – UMR 6164, F-35000, Rennes, France

Description: In this demonstrator we use Multi-Armed Bandit (MAB) Algorithms for the purpose of channel selection in IoT networks. These algoritms allow IoT devices avoiding overcrowded channels, i.e., with a high Packet Loss Ratio (PLR). In the proposed scenario, the learning is operated based on the acknowledgement transmitted by the base station. As a consequence, it does not require any cooperation between devices and consequently does not require any extra signaling.

Demonstration 3: Multi-source energy management for Long Range IoT nodes

Presenters: Philip-Dylan Gleonec, Wi6labs, Univ Rennes/IRISA

Description: Energy harvesters are used in Internet of Things (IoT) networks to provide more energy to the nodes and enhance their autonomy. However, the nodes must adapt their consumed energy to variable energy harvesting conditions. Typically, an energy budget estimation (EBE) algorithm is used to calculate an energy budget based on the current energy capabilities. In this demonstration, we will show the implementation and a comparison of multiple EBE algorithms on a real world LoRaWAN platform powered by different energy sources (indoor light, thermal, …). All nodes will be connected to a remote LoRaWAN application server through a LoRa gateway.

Demonstration 4: Partial reconfiguration on ARM/FPGA Platform for Vertical Handover for WIFI/Mimax

Presenters: Mohamad-Al-Fadl Rihani, Lebanese University, Faculty of Engineering III, Beirut, Lebanon and IETR, Jean-Christophe Prévotet,  Fabienne Nouvel, IETR-INSA, Rennes France, Mohamad Mroue, Lebanese University, Faculty of Engineering III, Beirut, Lebanon.

Description: In wireless networks, end-nodes are able to detect the presence of multiple standards and to switch between them is they are available on chip. In this context, it becomes interesting to design an on-line reconfigurable communication system thanks to a Vertical Handover Algorithm (VHA) that allows selecting the best wireless standard. In this demo, we propose to implement this mechanism using the Partial Reconfiguration (PR) technique on a SoC platform (ARM-FPGA). We apply VHA between WIFI and Wimax. The demo simulates the mobility of an end-node in a WIFI-WiMax network on a GUI Interface connected to the ZedBoard. On the SoC, the VHA senses specific parameters and decides accordingly to reconfigure a unified PHY layer before applying partial reconfiguration on the device.

Demonstration 5: Demonstration of a low-PAPR low-pilot overhead Reference Signal for the DFT-spread OFDM Modulation

Presenters: Arnaud Bouttier and Xavier Nourisson, Mitsubishi Electric R&D Centre Europe

Description: The demonstration deals with a new reference signal dedicated to the DFT-spread OFDM modulation. In order to benefit from low power fluctuations, the pilot is modulated like any DFT-s-OFDM symbol where a number of known pilot samples are inserted in front of information data prior DFT spreading. The symbol is built in such a way that the front part can be extracted to serve as a short OFDM reference symbol. The proposed pilot scheme is illustrated using a real-time FPGA hardware platform, including a hardware channel emulator, dedicated to the analysis of the DFT-spread OFDM modulation in a satellite context.

Demonstration 6: A Tight Integration of Multiple Radio Access Networks for Capacity Boosting and Traffic Steering

Presenters: Atm Shafiul Alam (MAC integration) and Marcin Filo (DCS-MAC)
5G Innovation Centre (5GIC), Institute for Communications Systems, University of Surrey, Guildford GU2 7XH, UK

Description: This demonstration is showcasing the innovation in SPEED-5G project, so-called eDSA (enhanced dynamic spectrum access) framework which offers a significant boost in system capacity, enabling dynamic traffic steering and offloading. This framework is based on dividing the MAC layer into higher MAC (HMAC) and lower MAC (LMAC). The scope of the demonstration is two-fold: (i) to showcase the feasibility of the concept of tight integration of multiple RATs at MAC-level for efficient heterogeneous spectrum resource usages; and (ii) to demonstrate a novel MAC solution, namely, Dynamic Channel Selection MAC (DCS-MAC), designed to operate in ultra-dense deployment scenarios characterized by excessive intra-RAT and inter-RAT interference.

Demonstration 7: Improved immunity to blockers and adjacent interferers for LoRa Gateways

Presenters: Patrick Savelli, b<>com, Mathieu Lagrange, b<>com.

In this demo, b<>com showcases the world first LoRa full SDR modem. This modem is built around two main elements:

  • A HW reconfigurable component that filters LoRa channels, performs IQ samples rate adaptation and detects whether a LoRa signal is transmitted in one of the available ISM channels
  •  An advanced receiver running in the Cloud that performs waveforms demodulation and frame decoding, and corrects multipath effects in the propagation channel

Signal processing algorithms implemented in this SDR modem are demonstrated through improved interferences immunity as compared to a commercial off-the-shelf LoRa gateway.

Demonstration 8: TDD MAC protocol implementation for dynamic spectrum access in the 5 GHz band

Presenters: Jérémy Estavoyer ( – CEA Leti, Grenoble

 This demo shows a TDD MAC protocol designed for 5G, able to operate on the unlicensed 5GHz band for carrier aggregation purpose. Based on a master-slave approach, it relies on a Filter Bank Multi Carrier modulation techniques which is well-known for the very low out-of-band emission levels it induces. Due to regulation constraints, this MAC is based on the transmission of superframes which are triggered by a listen-before-talk procedure. This feature is exploited to both fairly coexist with other systems within the same channel and to feed a machine learning-based algorithm for channel re-selection when the level of interference gets too high. The demonstration shows by means of real-life equipment and OTA signals, how the proposed MAC can coexist with WiFi in the 5 GHz band.


Demonstration 9: 5G NR SDR Platform supporting 80 Mhz Wide Radio Links

Presenters: Patrick ROBERT (, Benoit ROBERT, Fabrice ROBINET- SYRTEM S.a.r.l. ( Franconville France.

SYRTEM has developed a 5G NR ready SDR Platform to support easy implementation of 5G Demonstrations.
The Platform is constructed using easy to procure COTS Components and SYRTEM specifically developed SW(GPP) & FW (FPGA) supporting Components enabling GPP to FPGA offloading of computation intensive & real-time Waveforms Functions.
SYRTEM will showcase a 5G 300 Mbits/s Down-link transmission at 3.5 Ghz & 80 Mhz RF BW established between a gNB and a UE Demonstrator.
The UE Demonstrator offloads the LDPC decoding Function using an FPGA IP from Creonic.
Other Layer 1 Functions are executed on GPP using Open Air Interface SW Modules.
The SYRTEM Platform is being used in the context of the MassStart project (